code_generator_VHDL¶
The VHDL code generator.
Classes¶
|
The VHDL writer class. |
Module Contents¶
VHDLCodeGenerator¶
- VHDLCodeGenerator :module:
Inheritance: → VHDLCodeGenerator
The VHDL writer class.
This is the template for generating VHDL code.
- addAssignScalarleft, right, delay = 0, indentLevel = 0, inverted = False :module:
Add a signal assignment statement.
- param left:
Left-hand side signal
- type left:
str
- param right:
Right-hand side signal or expression
- type right:
str
- param delay:
Delay in picoseconds
- type delay:
int
- param indentLevel:
The indentation level
- type indentLevel:
int
- param inverted:
Whether to invert the right-hand side
- type inverted:
bool
- addAssignVectorleft, right, widthL, widthR, indentLevel = 0, inverted = False :module:
Add a vector slice assignment.
- param left:
Left-hand side signal
- type left:
str
- param right:
Right-hand side signal
- type right:
str
- param widthL:
Upper bound of slice
- type widthL:
str | int
- param widthR:
Lower bound of slice
- type widthR:
str | int
- param indentLevel:
The indentation level
- type indentLevel:
int
- param inverted:
Whether to invert the right-hand side
- type inverted:
bool
- addBelMapAttributeconfigBitValues, indentLevel = 0 :module:
Add the BEL mapping attribute as a VHDL comment.
- param configBitValues:
List of (name, count) pairs for configuration bits
- type configBitValues:
list[tuple[str, int]]
- param indentLevel:
The indentation level
- type indentLevel:
int
- addCommentcomment, onNewLine = False, end = '', indentLevel = 0 :module:
Add a VHDL comment to the generated code.
- param comment:
The comment text to add
- type comment:
str
- param onNewLine:
Whether to add the comment on a new line
- type onNewLine:
bool
- param end:
Additional text to append at the end
- type end:
str
- param indentLevel:
The indentation level for the comment
- type indentLevel:
int
- addComponentDeclarationForFilefileName :module:
Add a component declaration extracted from a VHDL file.
- param fileName:
Path to the VHDL file to extract the component from.
- type fileName:
str | Path
- returns:
1 if the component uses configuration bits; 0 otherwise.
- rtype:
int
- addConnectionScalarname, _reg = False, indentLevel = 0 :module:
Add a scalar signal declaration.
- param name:
Signal name
- type name:
str
- param _reg:
Register flag (unused in VHDL)
- type _reg:
bool
- param indentLevel:
The indentation level
- type indentLevel:
int
- addConnectionVectorname, startIndex, _reg = False, endIndex = 0, indentLevel = 0 :module:
Add a vector signal declaration.
- param name:
Signal name
- type name:
str
- param startIndex:
Start index (MSB)
- type startIndex:
int
- param _reg:
Register flag (unused in VHDL)
- type _reg:
bool
- param endIndex:
End index (LSB)
- type endIndex:
int
- param indentLevel:
The indentation level
- type indentLevel:
int
- addConstantname, value, indentLevel = 0 :module:
Add a constant declaration.
- param name:
Constant name
- type name:
str
- param value:
Constant value
- type value:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addDesignDescriptionEndindentLevel = 0 :module:
End the architecture declaration.
- param indentLevel:
The indentation level
- type indentLevel:
int
- addDesignDescriptionStartname, indentLevel = 0 :module:
Start the architecture declaration.
- param name:
Entity name
- type name:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addFlipFlopChainconfigBitCounter :module:
Add a flip-flop chain for configuration bits.
- param configBitCounter:
Total number of configuration bits.
- type configBitCounter:
int
- addHeadername, package = '', indentLevel = 0 :module:
Add VHDL entity header with standard libraries.
- param name:
Entity name
- type name:
str
- param package:
Additional package to include
- type package:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addHeaderEndname, indentLevel = 0 :module:
Add the entity end statement.
- param name:
Entity name
- type name:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addInstantiationcompName, compInsName, portsPairs, paramPairs = None, emulateParamPairs = None, indentLevel = 0 :module:
Add a component instantiation.
- param compName:
Component name
- type compName:
str
- param compInsName:
Instance name
- type compInsName:
str
- param portsPairs:
List of (port, signal) pairs for port mapping
- type portsPairs:
list[tuple[str, str]]
- param paramPairs:
List of (parameter, value) pairs for generic mapping
- type paramPairs:
list[tuple[str, str]] | None
- param emulateParamPairs:
Additional parameters (unused)
- type emulateParamPairs:
list[tuple[str, str]] | None
- param indentLevel:
The indentation level
- type indentLevel:
int
- addLogicEndindentLevel = 0 :module:
End the logic section (end statement).
- param indentLevel:
The indentation level
- type indentLevel:
int
- addLogicStartindentLevel = 0 :module:
Start the logic section (begin statement).
- param indentLevel:
The indentation level
- type indentLevel:
int
- addParametername, storageType, value, indentLevel = 0 :module:
Add a generic parameter declaration.
- param name:
Parameter name
- type name:
str
- param storageType:
Parameter type
- type storageType:
str
- param value:
Default value
- type value:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addParameterEndindentLevel = 0 :module:
End the generic parameter declaration section.
- param indentLevel:
The indentation level
- type indentLevel:
int
- addParameterStartindentLevel = 0 :module:
Start the generic parameter declaration section.
- param indentLevel:
The indentation level
- type indentLevel:
int
- addPortEndindentLevel = 0 :module:
End the port declaration section.
- param indentLevel:
The indentation level
- type indentLevel:
int
- addPortScalarname, io, _reg = False, attribute = '', indentLevel = 0 :module:
Add a scalar port declaration.
- param name:
Port name
- type name:
str
- param io:
Input/output direction
- type io:
IO
- param _reg:
Register flag (unused in VHDL)
- type _reg:
bool
- param attribute:
Additional attributes to add as a comment
- type attribute:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addPortStartindentLevel = 0 :module:
Start the port declaration section.
- param indentLevel:
The indentation level
- type indentLevel:
int
- addPortVectorname, io, msbIndex, _reg = False, attribute = '', indentLevel = 0 :module:
Add a vector port declaration.
- param name:
Port name
- type name:
str
- param io:
Input/output direction
- type io:
IO
- param msbIndex:
Most significant bit index
- type msbIndex:
int
- param _reg:
Register flag (unused in VHDL)
- type _reg:
bool
- param attribute:
Additional attributes to add as a comment
- type attribute:
str
- param indentLevel:
The indentation level
- type indentLevel:
int
- addPreprocElse_indentLevel = 0 :module:
Define to keep parity with Verilog.
VHDL does not support preprocessor directives.
- param _indentLevel:
Indentation level (unused).
- type _indentLevel:
int
- returns:
This function always raises an exception.
- rtype:
Never
- raises AssertionError:
Always, as VHDL doesn’t support preprocessing.
- addPreprocEndif_indentLevel = 0 :module:
Define to keep parity with Verilog.
VHDL does not support preprocessor directives.
- param _indentLevel:
Indentation level (unused).
- type _indentLevel:
int
- returns:
This function always raises an exception.
- rtype:
Never
- raises AssertionError:
Always, as VHDL doesn’t support preprocessing.
- addPreprocIfDef_macro, _indentLevel = 0 :module:
Define to keep parity with Verilog.
VHDL does not support preprocessor directives.
- param _macro:
Macro name (unused).
- type _macro:
str
- param _indentLevel:
Indentation level (unused).
- type _indentLevel:
int
- returns:
This function always raises an exception.
- rtype:
Never
- raises AssertionError:
Always, as VHDL doesn’t support preprocessing.
- addPreprocIfNotDef_macro, _indentLevel = 0 :module:
Define to keep parity with Verilog.
VHDL does not support preprocessor directives.
- param _macro:
Macro name (unused).
- type _macro:
str
- param _indentLevel:
Indentation level (unused).
- type _indentLevel:
int
- returns:
This function always raises an exception.
- rtype:
Never
- raises AssertionError:
Always, as VHDL doesn’t support preprocessing.
- addRegisterreg, regIn, clk = 'UserCLK', inverted = False, indentLevel = 0 :module:
Add a clocked register process.
- param reg:
Register output signal name
- type reg:
str
- param regIn:
Register input signal name
- type regIn:
str
- param clk:
Clock signal name
- type clk:
str
- param inverted:
Whether to invert the input
- type inverted:
bool
- param indentLevel:
The indentation level
- type indentLevel:
int
- addShiftRegisterindentLevel = 0 :module:
Add a shift register for configuration bits.
- param indentLevel:
The indentation level. Defaults to 0.
- type indentLevel:
int, optional